----------------------------------------------------------------------------------
-- INSTITUTION:    Xidian University
-- DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
-- 
-- Create Date:    16:53:58 02-14-2016 
-- Design Name:    SEG_CONVERTER 
-- Module Name:    SEG_CONVERTER
-- Project Name:   Timer
-- Target Devices: EP3C16F484C6
-- Tool versions:  Quartus II 13.1
-- Design Lauguage:VHDL
-- Dependencies:   -
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: DE0 Board Input Freguency = 50 MHz
--                      Destiny Output  Freguency =  1 Hz
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity SEG_CONVERTER is
	port(
		i_time_val: in STD_LOGIC_VECTOR (3 downto 0);
		i_sys_rst: in STD_LOGIC;	
		o_seg_display_val: out STD_LOGIC_VECTOR (6 downto 0) 	
	);
end entity SEG_CONVERTER;

architecture behavior of SEG_CONVERTER is
	signal r_seg_display_val: STD_LOGIC_VECTOR (6 downto 0);
begin
	process(i_sys_rst,i_time_val)	
		begin
			if (i_sys_rst = '1') then	
				r_seg_display_val <= "1111111";
			else
				case i_time_val is
					when "0000" => r_seg_display_val <= "1000000";
					when "0001" => r_seg_display_val <= "1111001";
					when "0010" => r_seg_display_val <= "0100100";
					when "0011" => r_seg_display_val <= "0110000";
					when "0100" => r_seg_display_val <= "0011001";
					when "0101" => r_seg_display_val <= "0010010";
					when "0110" => r_seg_display_val <= "0000010";
					when "0111" => r_seg_display_val <= "1111000";
					when "1000" => r_seg_display_val <= "0000000";
					when "1001" => r_seg_display_val <= "0010000";
					when others => r_seg_display_val <= "1111111";
				end case;	
			end if;	
	end process;
	o_seg_display_val <= r_seg_display_val;
end architecture behavior;
